Renesas Electronics 2305A-1DCG8 Clock Buffer 8-Pin SOIC
- RS Stock No.:
- 264-3451
- Mfr. Part No.:
- 2305A-1DCG8
- Manufacturer:
- Renesas Electronics
The image is for reference only, please refer to product details and specifications
Bulk discount available
View bulk pricing optionsSubtotal (1 pack of 5 units)*
TWD264.00
(exc. GST)
TWD277.20
(inc. GST)
FREE delivery for orders over NT$1,300.00
Temporarily out of stock
- Shipping from June 14, 2027
Need more? Click ‘Check delivery dates’ to find extra stock and lead times.
Units | Per unit | Per Pack* |
|---|---|---|
| 5 - 45 | TWD52.80 | TWD264.00 |
| 50 - 95 | TWD45.00 | TWD225.00 |
| 100 - 245 | TWD36.80 | TWD184.00 |
| 250 - 995 | TWD34.20 | TWD171.00 |
| 1000 + | TWD33.40 | TWD167.00 |
*price indicative
- RS Stock No.:
- 264-3451
- Mfr. Part No.:
- 2305A-1DCG8
- Manufacturer:
- Renesas Electronics
Specifications
Product overview and Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Maximum Input Frequency | 133MHz | |
| Mount Type | Surface | |
| Package Type | SOIC | |
| Pin Count | 8 | |
| Minimum Supply Voltage | 3V | |
| Maximum Supply Voltage | 4.6V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Standards/Approvals | No | |
| Series | IDT2305A | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Maximum Input Frequency 133MHz | ||
Mount Type Surface | ||
Package Type SOIC | ||
Pin Count 8 | ||
Minimum Supply Voltage 3V | ||
Maximum Supply Voltage 4.6V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Standards/Approvals No | ||
Series IDT2305A | ||
Automotive Standard No | ||
- COO (Country of Origin):
- PH
The Renesas Electronics high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133 MHz.
Phase-lock loop clock distribution
Distributes one clock input to one bank of five outputs
Power down mode
Available in SOIC package
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