Infineon S27KL0642DPBHI020 SDRAM 64 MB Surface, 24-Pin 8 bit FBGA-24 Ball
- RS Stock No.:
- 273-7512
- Mfr. Part No.:
- S27KL0642DPBHI020
- Manufacturer:
- Infineon
The image is for reference only, please refer to product details and specifications
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Add 1014 more to save TWD2,737.80
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TWD45,799.00
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TWD48,090.64
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Units | Per unit | Per Tray* | Saving |
|---|---|---|---|
| 338 - 676 | TWD135.50 | TWD45,799.00 | - |
| 1014 + | TWD132.80 | TWD44,886.40 | TWD2,737.80 |
*price indicative
- RS Stock No.:
- 273-7512
- Mfr. Part No.:
- S27KL0642DPBHI020
- Manufacturer:
- Infineon
Specifications
Product overview and Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Infineon | |
| Memory Size | 64MB | |
| Product Type | SDRAM | |
| Data Bus Width | 8bit | |
| Number of Bits per Word | 16 | |
| Maximum Clock Frequency | 200MHz | |
| Mount Type | Surface | |
| Package Type | FBGA-24 Ball | |
| Pin Count | 24 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 105°C | |
| Height | 1mm | |
| Series | S27K | |
| Standards/Approvals | No | |
| Width | 8mm | |
| Length | 6mm | |
| Supply Current | 360μA | |
| Automotive Standard | AEC-Q100 Grade 2 & 3 | |
| Minimum Supply Voltage | 1.8V | |
| Maximum Supply Voltage | 3.6V | |
| Select all | ||
|---|---|---|
Brand Infineon | ||
Memory Size 64MB | ||
Product Type SDRAM | ||
Data Bus Width 8bit | ||
Number of Bits per Word 16 | ||
Maximum Clock Frequency 200MHz | ||
Mount Type Surface | ||
Package Type FBGA-24 Ball | ||
Pin Count 24 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 105°C | ||
Height 1mm | ||
Series S27K | ||
Standards/Approvals No | ||
Width 8mm | ||
Length 6mm | ||
Supply Current 360μA | ||
Automotive Standard AEC-Q100 Grade 2 & 3 | ||
Minimum Supply Voltage 1.8V | ||
Maximum Supply Voltage 3.6V | ||
The Infineon DRAM is a high speed CMOS, self refresh DRAM, with HYPERBUS interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS interface master. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as Pseudo Static RAM.
200 MHz maximum clock rate
Data throughput up to 400 MBps
Bidirectional read write data strobe
Automotive AEC Q100 Grade 2 and 3
Optional DDR centre aligned read strobe
DDR transfers data on both edges of the clock
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