Toshiba 74HC573D 8-Bit Octal D Type Latch, Transparent, D Type Flip-Flop, 20-Pin SOIC
- RS Stock No.:
- 171-3106
- Mfr. Part No.:
- 74HC573D
- Manufacturer:
- Toshiba
The image is for reference only, please refer to product details and specifications
Currently unavailable
We don't know if this item will be back in stock, RS intend to remove it from our range soon.
- RS Stock No.:
- 171-3106
- Mfr. Part No.:
- 74HC573D
- Manufacturer:
- Toshiba
Specifications
Product overview and Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Toshiba | |
| Product Type | Octal D Type Latch | |
| Logic Family | 74HC | |
| Latch Mode | Transparent | |
| Logic Function | D Type | |
| Number of Bits | 8 | |
| Number of Channels | 8 | |
| Output Type | D Type Flip-Flop | |
| Polarity | Inverting | |
| Mount Type | Surface | |
| Minimum Supply Voltage | 2V | |
| Package Type | SOIC | |
| Maximum Supply Voltage | 6V | |
| Pin Count | 20 | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Series | 74HC | |
| Length | 13.1mm | |
| Standards/Approvals | No | |
| Height | 2.25mm | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Toshiba | ||
Product Type Octal D Type Latch | ||
Logic Family 74HC | ||
Latch Mode Transparent | ||
Logic Function D Type | ||
Number of Bits 8 | ||
Number of Channels 8 | ||
Output Type D Type Flip-Flop | ||
Polarity Inverting | ||
Mount Type Surface | ||
Minimum Supply Voltage 2V | ||
Package Type SOIC | ||
Maximum Supply Voltage 6V | ||
Pin Count 20 | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Series 74HC | ||
Length 13.1mm | ||
Standards/Approvals No | ||
Height 2.25mm | ||
Automotive Standard No | ||
The 74HC573D is a high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gateC2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. These 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE).When the OE input is high, the eight outputs are in a high impedance state. All inputs are equipped with protection circuits against static discharge or transient excess voltage
High speed: tpd = 13 ns (typ.) at VCC = 6.0 V
Low power dissipation: ICC = 4.0 μA (max) at Ta = 25
Balanced propagation delays: tPLH ≈ tPHL
Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V
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