- RS Stock No.:
- 216-6232
- Mfr. Part No.:
- 8SLVP1208ANBGI
- Manufacturer:
- Renesas Electronics
Temporarily out of stock - back order for despatch 10/02/2025, delivery within 6 working days
Added
Price (VAT excluded) Each (In a Tray of 490)
TWD185.80
(exc. GST)
TWD195.09
(inc. GST)
Units | Per unit | Per Tray* |
490 - 490 | TWD185.80 | TWD91,042.00 |
980 + | TWD181.80 | TWD89,082.00 |
*price indicative |
- RS Stock No.:
- 216-6232
- Mfr. Part No.:
- 8SLVP1208ANBGI
- Manufacturer:
- Renesas Electronics
Product overview and Technical data sheets
Legislation and Compliance
Product Details
The Renesas Electronics 8SLVP1208 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVP1208 is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1208 ideal for those clock distribution applications demanding well-defined performance and repeatability.
Eight low skew, low additive jitter LVPECL output pairs
Two selectable, differential clock input pairs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input (input select)
Output skew: 28ps (typical)
Propagation delay: 410ps (maximum)
Low additive phase jitter, RMS: 54.1fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz)
Two selectable, differential clock input pairs
Differential pairs can accept the following differential input
levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
LVCMOS interface levels for the control input (input select)
Output skew: 28ps (typical)
Propagation delay: 410ps (maximum)
Low additive phase jitter, RMS: 54.1fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz)
For products that are Customized and under Non-cancellable & Non-returnable, Sales & Conditions apply.
Specifications
Attribute | Value |
---|---|
Logic Family | LVPECL |
Logic Function | Clock Buffer |
Input Signal Type | LVPECL |
Number of Clock Inputs | 4 |
Package Type | LFCSP |
Pin Count | 28 |