Renesas Electronics 8305AGLF Clock Buffer, 16-Pin 4 TSSOP
- RS Stock No.:
- 216-6205
- Mfr. Part No.:
- 8305AGLF
- Manufacturer:
- Renesas Electronics
The image is for reference only, please refer to product details and specifications
Bulk discount available
Subtotal (1 tube of 96 units)*
TWD16,128.00
(exc. GST)
TWD16,934.40
(inc. GST)
FREE delivery for orders over NT$1,300.00
Last RS stock
- Final 96 unit(s), ready to ship from another location
Units | Per unit | Per Tube* |
|---|---|---|
| 96 - 96 | TWD168.00 | TWD16,128.00 |
| 192 - 288 | TWD164.60 | TWD15,801.60 |
| 384 + | TWD161.30 | TWD15,484.80 |
*price indicative
- RS Stock No.:
- 216-6205
- Mfr. Part No.:
- 8305AGLF
- Manufacturer:
- Renesas Electronics
Specifications
Product overview and Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Renesas Electronics | |
| Product Type | Clock Buffer | |
| Mount Type | Surface | |
| Package Type | TSSOP | |
| Pin Count | 16 | |
| Minimum Supply Voltage | 1.5V | |
| Maximum Supply Voltage | 3.3V | |
| Minimum Operating Temperature | 0°C | |
| Maximum Operating Temperature | 70°C | |
| Width | 3.3 mm | |
| Height | 0.9mm | |
| Series | 8305A | |
| Standards/Approvals | No | |
| Length | 4mm | |
| Number of Outputs | 4 | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Renesas Electronics | ||
Product Type Clock Buffer | ||
Mount Type Surface | ||
Package Type TSSOP | ||
Pin Count 16 | ||
Minimum Supply Voltage 1.5V | ||
Maximum Supply Voltage 3.3V | ||
Minimum Operating Temperature 0°C | ||
Maximum Operating Temperature 70°C | ||
Width 3.3 mm | ||
Height 0.9mm | ||
Series 8305A | ||
Standards/Approvals No | ||
Length 4mm | ||
Number of Outputs 4 | ||
Automotive Standard No | ||
The Renesas Electronics ICS8305 is a low skew, 1-to-4, Differential/ LVCMOS-to-LVCMOS/LVTTL Fanout Buffer. The ICS8305 has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state.
Four LVCMOS / LVTTL outputs, 7 output impedance
Selectable differential or LVCMOS / LVTTL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
Maximum output frequency: 350MHz
Output skew: 35ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
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