Microchip AT91SAM9G25-BFU ARM926EJ-S Microprocessor SAM9G25 32 bit ARM 400 MHz 247-Pin VFBGA
- RS Stock No.:
- 775-375
- Mfr. Part No.:
- AT91SAM9G25-BFU
- Manufacturer:
- Microchip
N
Subtotal (1 tray of 168 units)*
TWD46,855.20
(exc. GST)
TWD49,197.12
(inc. GST)
Stock information currently inaccessible - Please check back later
Units | Per unit | Per Tray* |
|---|---|---|
| 168 + | TWD278.90 | TWD46,855.20 |
*price indicative
- RS Stock No.:
- 775-375
- Mfr. Part No.:
- AT91SAM9G25-BFU
- Manufacturer:
- Microchip
Specifications
Product overview and Technical data sheets
Legislation and Compliance
Product Details
Find similar products by selecting one or more attributes.
Select all | Attribute | Value |
|---|---|---|
| Brand | Microchip | |
| Product Type | Microprocessor | |
| Series | SAM9G25 | |
| Device Core | ARM926EJ-S | |
| Data Bus Width | 32bit | |
| Instruction Set Architecture | ARM | |
| Maximum Clock Frequency | 400MHz | |
| Interface Type | ADC, LCD, SPI, USART, USB | |
| Mount Type | Surface Mount | |
| Minimum Supply Voltage | 0.9V | |
| Package Type | VFBGA | |
| Pin Count | 247 | |
| Maximum Supply Voltage | 1.1V | |
| Minimum Operating Temperature | -40°C | |
| Maximum Operating Temperature | 85°C | |
| Number of Cores | 1 | |
| Automotive Standard | No | |
| Select all | ||
|---|---|---|
Brand Microchip | ||
Product Type Microprocessor | ||
Series SAM9G25 | ||
Device Core ARM926EJ-S | ||
Data Bus Width 32bit | ||
Instruction Set Architecture ARM | ||
Maximum Clock Frequency 400MHz | ||
Interface Type ADC, LCD, SPI, USART, USB | ||
Mount Type Surface Mount | ||
Minimum Supply Voltage 0.9V | ||
Package Type VFBGA | ||
Pin Count 247 | ||
Maximum Supply Voltage 1.1V | ||
Minimum Operating Temperature -40°C | ||
Maximum Operating Temperature 85°C | ||
Number of Cores 1 | ||
Automotive Standard No | ||
- COO (Country of Origin):
- TW
The Microchip versatile microprocessor is designed for multi-tasking applications, offering efficient handling of both 32-bit ARM and 16-bit Thumb instruction sets, Ideal for both performance and code density optimisation.
Supports Harvard cached architecture for improved performance
Incorporates a Memory Management Unit for enhanced memory control
Features separate instruction and data AHB bus interfaces
Allows external coprocessors to accelerate specific hardware functions