Cypress Semiconductor S27KS0641DPBHI020, SDRAM 64Mbit Surface Mount, 333Mbit/s, 24-Pin FBGA

Product overview and Technical data sheets
Legislation and Compliance
RoHS Certificate of Compliance
Product Details

3.0 V I/O, 11 bus signals
Single ended clock (CK)
1.8 V I/O, 12 bus signals
Differential clock (CK, CK#)
Chip Select (CS#)
8-bit data bus (DQ[7:0])
Read-Write Data Strobe (RWDS)
Bidirectional Data Strobe / Mask
Output at the start of all transactions to indicate refresh latency
Output during read transactions as Read Data Strobe
Input during write transactions as Write Data Mask
During read transactions RWDS is offset by a second clock, phase shifted from CK
The Phase Shifted Clock is used to move the RWDS transition edge within the read data eye
Up to 333 MBps
Double-Data Rate (DDR) - two data transfers per clock
166 MHz clock rate (333 MBps) at 1.8 V VCC
100 MHz clock rate (200 MBps) at 3.0 V VCC
Sequential burst transactions
Configurable Burst Characteristics
Wrapped burst lengths:
16 bytes (8 clocks)
32 bytes (16 clocks)
64 bytes (32 clocks)
128 bytes (64 clocks)
Linear burst
Hybrid option - one wrapped burst followed by linear burst
Wrapped or linear burst type selected in each transaction
Configurable output drive strength
Low Power Modes
Deep Power Down
24-ball FBGA

Attribute Value
Memory Size 64Mbit
Organisation 8M x 8 bit
Data Rate 333Mbit/s
Data Bus Width 8bit
Number of Bits per Word 8bit
Maximum Random Access Time 36ns
Number of Words 8M
Mounting Type Surface Mount
Package Type FBGA
Pin Count 24
Dimensions 8 x 6 x 0.8mm
Height 0.8mm
Length 8mm
Maximum Operating Temperature +85 °C
Minimum Operating Supply Voltage 1.7 V
Maximum Operating Supply Voltage 1.95 V
Minimum Operating Temperature -40 °C
Width 6mm
279 In stock for delivery within 6 working days
Price (VAT excluded) Each (In a Pack of 3)
TWD 138.70
(exc. GST)
TWD 145.60
(inc. GST)
Per unit
Per Pack*
3 +
*price indicative
Packaging Options: